The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths below 100 nanometer (nm), high reliability and increased manufacturing throughput. When the gate length of a conventional planar metal oxide semiconductor field effect transistor (MOSFET) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and process issues make scaling down device features of conventional MOSFETs difficult. The FinFET design relies upon a thin vertical silicon “fin” to help control current leakage through the transistor in the “off” stage and a double gate structure to control short channel effects.
FIGS. 1A and 1B illustrate top views of a typical FinFET. As shown, gate 101 is wrapped around the top and sides of fin 103. Source 105 is formed at one end of fin 103, and drain 107 is formed at the other end. Gate spacers (not shown) are formed all around the gate. However, spacer formation on FinFETs is difficult, since the spacer must be completely removed from the fin while remaining on the gate. Forming a conformal layer over the gate and fins and etching it back to form spacers leaves material in the lower area and/or damages the spacers. Attempts to optimize the etching of the spacers have not proven successful.
A need therefore exists for methodology to facilitate fabrication of gate spacers on FinFETs employing conventional etching techniques.